Integrated circuit devices, such as integrated circuit memory devices and integrated circuit logic devices, are widely used in consumer and commercial applications.
Recently, merged memory and logic (MML) integrated circuits have been developed. MML integrated circuits generally include a large capacity memory and a large logic block that are merged in one integrated circuit. The large capacity memory is generally divided into a plurality of memory banks, also referred to as "memories". The logic block may also be referred to as a "logic circuit" or simply as a "logic". Thus, an MML integrated circuit can replace discrete memory and logic chips that are used in personal computers and other consumer and commercial devices.
MML integrated circuits present new challenges for control of the multiple memory banks. More specifically, FIG. 1 is a schematic block diagram of a conventional synchronous dynamic random access memory (SDRAM) having a plurality of memory banks. An SDRAM 100 having two banks, i.e., banks A and B 103 and 105 is shown in FIG. 1.
Referring to FIG. 1, a conventional SDRAM 100 includes command input pads (also referred to as pins) used in common for the banks A and B 103 and 105, i.e., one row address strobe signal RAS input pin P1, one column address strobe signal CAS input pin P2, and one write enable signal WE input pin P3. Also, a conventional SDRAM 100 includes a bank selection bit (BADDR) input pin P5. Bank A 103 or bank B 105 is selected according to the logic state of the bank selection bit BADDR. That is, the controller 101 recognizes signals RAS, CAS and WE received through the command input pins P1, P2 and P3 as commands for the bank A 103 or bank B 105 according to the logic state of the bank selection bit BADDR.
In a conventional SDRAM 100, addresses ADDR0-ADDRi for addressing the bank A 103 or bank B 105, i.e., row and column addresses, are received through identical address input pins P40 through P4i, and multiplexed in the controller 101 in the chip. Also, in a conventional SDRAM 100, input or output data DQ0-DQk are received or generated through identical pins P10.phi. through P10k and multiplexed in an input/output unit 107. In
FIG. 1, a signal CLK received through the input pin P6 is a system clock signal, a signal CKE received through the input pin P7 is a clock enable signal, a signal CS received through the input pin P8 is a chip selection signal, and a signal DQM received through the input pin P9 is a data input/output mask signal.
The above SDRAM architecture is well known to one skilled in the art. FIG. 2 is a timing diagram of a read operation of a conventional SDRAM of FIG. 1. Unfortunately, the performance of an MML integrated circuit may degrade when the above SDRAM and a logic circuit are merged in an MML integrated circuit.
MML integrated circuits also present new challenges for the testing thereof. In particular, the MML integrated circuit generally provides a large number of internal data pads between the memory block and the logic block. For example, up to 256 or more internal data lines may be provided. Since many of these internal data lines are not brought out to external MML integrated circuit pads, it may be difficult to access all of the internal data lines in order to test the memory block.
Stated differently, in order to test a conventional memory integrated circuit, test equipment is connected to the pads of the memory integrated circuit. However, the memory block in an MML integrated circuit may be difficult to test because the memory is connected to the external pads through the logic block. Accordingly, additional pads may be needed to test the memory of the MML integrated circuit. Unfortunately, the addition of large numbers of test pads may increase the cost, size and/or complexity of an MML integrated circuit.